1. Field of the Invention
This invention relates generally to the cell structure, device configuration and fabrication process of power semiconductor devices. More particularly, this invention relates to a novel and improved cell configuration and processes to manufacture MOSFET device with an improved drain-gate clamping diode for avalanche protection by providing the GD clamp diode with lower avalanche breakdown voltage than the trenched MOSFET.
2. Description of the Related Art
Conventional technologies still have technical difficulties in providing effective avalanche protection for the semiconductor power devices. Several circuit structures by implementing Zener diodes for clamping the gate-source and gate-drain voltage for avalanche protection are disclosed. But these circuits and methods still have their disadvantages and limitations.
In U.S. Pat. No. 5,079,608 a the lateral N+/P Zener diodes disposed between the gate and drain of a planar MOSFET are implemented as voltage clamp diodes for avalanche protection. FIG. 1A is a circuit diagram and FIG. 1B is a side cross sectional view for showing the device implemented with the G-D clamp diodes. The clamp diodes have avalanche voltage lower than that of the drain/source of the MOSFET device. When the drain/source voltage rises above the avalanche voltage of the drain/gate diodes, a current flows through the claim diodes. The current develops a voltage across the gate/source resistor and the voltage serves a function to turn on the MOSFET. The gate/source voltage continues to increase until the MOSFET transmits all of the stored inductive energy. The G-D clamp diodes however are built as part of the floating ring structure and such structure is not suitable of MOSFET device implemented with the field plate in the termination area.
U.S. Pat. No. 5,631,187 discloses a planar MOSFET that includes N+/P polysilicon Zener diodes formed between the gate and drain as the voltage clamp diodes. A shunt resistor is further formed between the gate and source for avalanche protection. FIG. 1C is a circuit diagram and FIG. 1D is a side cross sectional view for showing the device implemented with the G-D clamp diodes with the shunt resistor connected between the gate and the source. The protection circuit as disclosed in this invention however suffers from a high leakage current between the gate and source due to the resistor shunt connected between the gate and the source of the MOSFET.
Therefore, there is still a need in the art of the semiconductor device fabrication, particularly for trenched power semiconductor design and fabrication, to provide a novel cell structure, device configuration and fabrication process that would resolve these difficulties and design limitations. Specifically, it is desirable to provide effective over-voltage protection to reduce a likelihood of device damages caused by avalanche. In the meantime, it is also desirable to eliminate the problems and limitations as that encountered in the conventional protection circuits. Additionally, it is desirable to overcome the problems caused by the weak spot due to the presence of a thin oxide layer disposed underneath the Zener diode.